my $cell = $module->find_cell ('cellname');
DESCRIPTIONA Verilog::Netlist::Cell object is created by Verilog::Netlist for every instantiation in the current module.
ACCESSORSSee also Verilog::Netlist::Subclass for additional accessors and methods.
- Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.
- Delete the cell from the module it's under.
- True if the cell is a gate primitive instantiation (buf/cmos/etc), but not a UDP.
- Pointer to the module the cell is in.
- The instantiation name of the cell.
- Reference to the Verilog::Netlist the cell is under.
- List of Verilog::Netlist::Pin connections for the cell.
- List of name sorted Verilog::Netlist::Pin connections for the cell.
- Reference to the Verilog::Netlist::Module the cell instantiates. Only valid after the design is linked.
- The module name the cell instantiates (under the cell).
MEMBER FUNCTIONSSee also Verilog::Netlist::Subclass for additional accessors and methods.
- Checks the cell for errors. Normally called by Verilog::Netlist::lint.
- Creates a new Verilog::Netlist::Pin connection for this cell.
- Returns all Verilog::Netlist::Pin connections for this cell.
- Prints debugging information for this cell.
DISTRIBUTIONVerilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from <http://www.veripool.org/verilog-perl>.
Copyright 2000-2016 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.