altera_avgen(4) driver for generic Altera Avalon-bus-attached, memory-mapped devices

SYNOPSIS

device altera_avgen

In /boot/device.hints hint.altera_avgen.0.at=nexus0 hint.altera_avgen.0.maddr=0x7f00a000 hint.altera_avgen.0.msize=20 hint.altera_avgen.0.width=4 hint.altera_avgen.0.fileio=rw hint.altera_avgen.0.devname=berirom

DESCRIPTION

The device driver provides generic support for memory-mapped devices on the Altera Avalon bus. device.hints entries configure the address, size, I/O disposition, and /dev device node name that will be used. The open(2), read(2), write(2), and mmap(2) system calls (and variations) may be used on device nodes, subject to constraints imposed using device.hints entries. Although reading and writing mapped memory is supported, does not currently support directing device interrupts to userspace.

A number of device.hints sub-fields are available to configure device instances:

maddr
base physical address of the memory region to export; must be aligned to width
msize
length of the memory region export; must be aligned to width
width
Granularity at which read(2) and write(2) operations will be performed. Larger requests will be broken down into width -sized operations; smaller requests will be rejected. I/O operations must be aligned to width
fileio
allowed file descriptor operations; r authorizes read(2); w authorizes write(2).
mmapio
allowed mmap(2) permissions; w authorizes PROT_WRITE r authorizes PROT_READ x authorizes PROT_EXEC
devname
specifies a device name relative to /dev
devunit
specifies a device unit number; no unit number is used if this is unspecified.

HISTORY

The device driver first appeared in Fx 10.0 .

AUTHORS

The device driver and this manual page were developed by SRI International and the University of Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) (Do CTSRD Dc , ) as part of the DARPA CRASH research programme. This device driver was written by An Robert N. M. Watson .

BUGS

is intended to support the writing of userspace device drivers; however, it does not permit directing interrupts to userspace, only memory-mapped I/O.

supports only a nexus bus attachment, which is appropriate for system-on-chip busses such as Altera's Avalon bus. If the target device is off of another bus type, then additional bus attachments will be required.