altera_sdcard(4) driver for the Altera University Program Secure Data Card IP Core


device altera_sdcard

In /boot/device.hints hint.altera_sdcardc.0.maddr=0x7f008000 hint.altera_sdcardc.0.msize=0x400


The device driver provides support for the Altera University Program Secure Data Card (SD Card) IP Core device. A controller device, altera_sdcardcX will be attached during boot. Inserted disks are presented as disk(9) devices, altera_sdcardX corresponding to the controller number.


The current version of the driver supports the SD Card IP core as described in the August 2011 version of Altera's documentation. The core supports only cards up to 2G (CSD 0); larger cards, or cards using newer CSD versions, will not be detected. The IP core has two key limitations: a lack of interrupt support, requiring timer-driven polling to detect I/O completion, and support for only single 512-byte block read and write operations at a time. The combined effect of those two limits is that the system clock rate, HZ must be set to at least 200 in order to accomplish the maximum 100KB/s data rate supported by the IP core.


The device driver first appeared in Fx 10.0 .


The device driver and this manual page were developed by SRI International and the University of Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) (Do CTSRD Dc , ) as part of the DARPA CRASH research programme. This device driver was written by An Robert N. M. Watson .


contains a number of work-arounds for IP core bugs. Perhaps most critically, ignores the CRC error bit returned in the RR1 register, which appears to be unexpectedly set by the IP core.

uses fixed polling intervals are used for card insertion/removal and I/O completion detection; an adaptive strategy might improve performance by reducing the latency to detecting completed I/O. However, in our experiments, using polling rates greater than 200 times a second did not improve performance.

supports only a nexus bus attachment, which is appropriate for system-on-chip busses such as Altera's Avalon bus. If the IP core is configured off of another bus type, then additional bus attachments will be required.