fnf(1) translate from FNF format to other formats


fnf [options]


FNF (Free Netlist Format) is an elaborated, hierarchical, register transfer level (RTL) netlist format used to communicate design information between frontend EDA tools.

The FNF tool translates an FNF netlist to Verilog, VHDL, C, and NuSMV.


Options are processed in the order they are received.

-h OR -help Prints this information then exits.

-read_fnf file Read in an FNF netlist.

-write_fnf file Write out an FNF netlist.

-write_nusmv file Write out an NuSMV description.

-write_verilog file Write out a Verilog netlist.

-write_vhdl file Write out a VHDL netlist.

-write_c file

Write out a C model.
Appends '.c' and '.h' to file name.

-write_jhdl class

Write out a JHDL netlist.
Appends .java to class name.


Building an FNF netlist from Verilog using Icarus:

      $ iverilog -Wall -t fnf -o my_netlist.fnf my_verilog.v
Use FNF to produce a Verilog and C model:

      $ fnf -read_fnf my_netlist.fnf -write_verilog my_netlist.v -write_c my_netlist
Use FNF to produce an NuSMV model:

      $ fnf -read_fnf my_netlist.fnf -write_nusmv my_netlist.smv
Use FNF to produce another FNF netlist:

      $ fnf -read_fnf my_netlist.fnf -write_fnf my_netlist2.fnf


  • No tristate support.
  • No memory support.
  • No division or modulo operators.

Icarus Verilog FNF Code Generator

  • Assumes ports and named signals have [n:0] ordering.
  • "always" blocks are constrained to the Icarus Verilog synthesizable subset.
  • All register clocks and asynchronous resets must be senitive on the rising edge. WARNING: No errors will be issued if a design contains "negedge".
  • All arithmetic operations must be unsigned. WARNING: No errors will be issued if a design contains signed operations.
  • Multipliers can not be embbeded in concatenations.

Verilog and VHDL Model Writer

  • Netlist is flat.

NuSMV Model Writer

- 2-value model.
No X's or Z's.
Inputs assumed to init to 0.
Registers are initialized to 0.




Tom Hawkins


Copyright (C) 2004-2005 Tom Hawkins