#if defined GG_HAVE_INT64
#if defined GG_LITTLE_ENDIAN
#if defined GG_BIG_ENDIAN
DESCRIPTIONThe GG_HAVE_INT64 macro is defined on 64-bit architectures where 64-bit integer values function as normal integer values with respect to C operations. Otherwise it is not defined.
The GG_LITTLE_ENDIAN or GG_BIG_ENDIAN are defined, respectively, when the architecture stores values in little or big endian order. One of the two will be defined, the other undefined, accordingly.
SWAR stands for SIMD Within A Register. The most well known example of SWAR is Intel MMX technology.
ggGetSwarType tells which specific SWAR instruction sets the CPU implements. This is useful to choose at runtime a machine-specific implementation of a very calculation-intensive routine. SWAR detection is done once during ggInit(3) and the value is cached for future use, thus it should be fast enough to choose implementations on the fly. However, due to this, SMP machines must have identical feature sets in all processors in order to ensure accurate results (see the GG_OPTS option description below.)
RETURN VALUEggGetSwarType returns an integer in which each bit set means that a specific SWAR instruction set is available. The integer value may be 32 bits long or 64 bits long, depending on whether LibGG was compiled for a 32-bit or 64-bit machine, as per the GG_HAVE_INT64 macro.
RECOGNIZED SWARSThe following flags are defined for all architectures. All of these flags can be OR'ed and are exclusive even between architectures. Note at this stage of development some of these SIMD sets are not yet detected correctly.
The CPU can run a vanilla C program. (hopefully! :-)
The CPU can perform 32-bit math fast enough to give an advantage over
16-bit math for software SWAR implementations. Almost all computers
will have this capability today.
The CPU has an AltiVec matrix coprocessor (Motorola G4.)
The CPU supports Intel Streaming SIMD Extensions.
The CPU supports Intel Streaming SIMD Extensions Version 2.
The CPU supports Intel Streaming SIMD Extensions Version 3.
The CPU supports Intel Multimedia Extensions.
The CPU supports Cyrix enhancements to Intel Multimedia Extensions.
The CPU supports AMD 3DNOW! instructions.
The CPU supports AMD Advanced 3DNOW! instructions.
The CPU supports PA-RISC MAX Instructions.
The CPU supports Microunity Mediaprocessor SIGD instructions.
Additionally, 64 bits architectures define the following flags:
The CPU can perform 64-bit math fast enough to give an advantage over
32-bit and 16-bit math for software SWAR implementations.
The CPU supports DEC (Compaq) Alpha Motion Video Instructions.
The CPU supports PA-RISC MAX2 Instructions.
The CPU supports MIPS Digital Media Extension (MaDMaX) Instructions.
The CPU supports SUN Microprocessor Architecture for Java Computing.
The CPU supports the SUN Visual Instruction Set
ENVIRONMENT VARIABLEIf the "-banswar=0xhexnumber" option is present in the GG_OPTS environment variable when ggInit is first called, bits set in the 0xhexnumber field will not be presented to the application in the return value of ggGetSwarType. This feature can be used for performance benchmarking, to disable the use of certain SWAR implementations. It may also be used if a multiproccesor machine mis-detects the usable SWAR instruction set because the processors are not identical.
BUGSNo support is currently implemented for PDP endian machines.
SWAR detection code is incomplete for many architectures, and as such LibGG may may fail to detect SWAR in the CPU.