pp-trace(1) manual page for pp-trace 3.4


OVERVIEW: pp-trace.

USAGE: pp-trace [options] <source0> [... <sourceN>] <arguments to be passed to front end>...


-asm-verbose - Add comments to directives.
-bounds-checking-single-trap - Use one trap block per function
-cppfname=<function name> - Specify the name of the generated function
-cppfor=<string> - Specify the name of the thing to generate
-cppgen - Choose what kind of output to generate
- Generate a complete program
- Generate a module definition
- Generate contents of a module
- Generate a function definition
- Generate all function definitions
- Generate an inline function
- Generate a variable definition
- Generate a type definition
-disable-debug-info-verifier -
-disable-spill-fusing - Disable fusing of spill code into instructions
-enable-correct-eh-support - Make the -lowerinvoke pass insert expensive, but correct, EH code
-enable-load-pre -
-enable-objc-arc-opts - enable/disable all ARC Optimizations
-enable-tbaa -
-fatal-assembler-warnings - Consider warnings as error
-fdata-sections - Emit data into separate sections
-ffunction-sections - Emit functions into separate sections
-help - Display available options (-help-hidden for more)
-ignore=<string> - Ignore callbacks, i.e. "Callback1, Callback2...".
-internalize-public-api-file=<filename> - A file containing list of symbol names to preserve
-internalize-public-api-list=<list> - A list of symbol names to preserve
-join-liveintervals - Coalesce copies (default=true)
-limit-float-precision=<uint> - Generate low-precision inline sequences for some float libcalls
-mc-x86-disable-arith-relaxation - Disable relaxation of arithmetic instruction for X86
-mips16-hard-float - MIPS: mips16 hard float enable.
-mno-ldc1-sdc1 - Expand double precision loads and stores to their single precision counterparts
-nvptx-sched4reg - NVPTX Specific: schedule for register pressue
-output=<string> - Output trace to the given file name or '-' for stdout.
-pre-RA-sched - Instruction schedulers available (before register allocation):
- VLIW scheduler
- Bottom-up register pressure aware list scheduling which tries to balance ILP and register pressure
- Bottom-up register pressure aware list scheduling which tries to balance latency and register pressure
- Similar to list-burr but schedules in source order when possible
- Bottom-up register reduction list scheduling
- Linearize DAG, no scheduling
- Fast suboptimal list scheduling
- Best scheduler for the target
-print-after-all - Print IR after each pass
-print-before-all - Print IR before each pass
-print-machineinstrs=<pass-name> - Print machine instrs
-regalloc - Register allocator to use
- pick register allocator based on -O option
- basic register allocator
- fast register allocator
- greedy register allocator
- PBQP register allocator
-spiller - Spiller to use: (default: standard)
- trivial spiller
- inline spiller
-stats - Enable statistics output from program (available with Asserts)
-time-passes - Time each pass, printing elapsed time for each on exit
-verify-dom-info - Verify dominator info (time consuming)
-verify-loop-info - Verify loop info (time consuming)
-verify-regalloc - Verify during register allocation
-verify-region-info - Verify region info (time consuming)
-verify-scev - Verify ScalarEvolution's backedge taken counts (slow)
-version - Display the version of this program
-x86-asm-syntax - Choose style of code to emit from X86 backend:
- Emit AT&T-style assembly
- Emit Intel-style assembly