rd(1) Register manipulation commands

Other Alias



rd [[c [n]]|d|u]

rm register-name new-contents

ef <address>


The rd command is used to display the contents of processor and coprocessor registers. Without any arguments, the rd command displays the contents of the general register set at the point at which the kernel debugger was entered. If the bt* or pid commands have been used to change the current process then rd and rm may not be able to display any registers. coprocessor number, while 'd' option is not valid for XScale platform.

On IA32 and IA64, with the 'c' argument, the processor control registers %cr0, %cr1, %cr2 and %cr4 are displayed, while with the 'd' argument the processor debug registers are displayed. If the 'u' argument is supplied, the registers for the current task as of the last time the current task entered the kernel are displayed.

On XScale, 'c' argument is used to display the all coprocessor control registers or specified coprocessor registers by argumnet 'n'. Argument 'u' is used to display the registers for the current task as of the last time the current task entered the kernel. Argument 'd' is not supported.

On ix86, the rm command allows modification of a register. The following register names are valid: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eip, and %ebp. Note that if two '%' symbols are used consecutively, the register set displayed by the 'u' argument to the rd command is modified.

The debug registers, dr0 through dr3 and both dr6 and dr7 can also be modified with the rm command.

On sparc64, the valid registers are named %g0 through %g7, %l0 through %l7, %o0 through %o7, and %i0 through %i7, with the exceptions that %o6 is called %sp and that %i6 is called %fp. The registers %tstate, %tpc, %tnpc, %y, and %fprs provide state information at the time the system entered kdb. Additionally, when viewing registers, two convenience names are provided: %&regs shows the address on the stack of the current registers, and %csp shows the current stack pointer within kdb itself.

While on XScale, both the cpu registers and most coprocessor registers can be be modified. register-name can be followings like r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, cpsr to address cpu registers. For the coprocessor registers in XSacle, either alias name or Cpcc[CRndd[CRmbb[Opaa]]] can be used to address the register in coprocessor cc with CRn=dd, CRm=bb and opcode2=aa. All aa, bb, cc, dd can be 1 or 2 decimal digitals, the default value is 0 when any of them is omitted. Name acc0_h and acc0_l are used to identify the high byte and low word of accumulator in coprocessor 0.

On IA64, the parameter to rd can be d (debug registers), u (user registers at most recent entry to kernel), i (interrupt registers), %isr (current interrupt status), s (stacked registers), k (kernel registers). You can also specify these individual registers - psr, ifs, ip, unat, pfs, rsc, rnat, bsps, pr, ldrs, ccv, fpsr, b0, b6, b7, r1, r2, r3, r8, r9, r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30, r31. rm can change any of the individual registers or the stacked registers.

The ef command displays an exception frame at the specified address.


Currently the rm command will not allow modification of the control registers.

Currently neither the rd command nor the rm command will display or modify the model specific registers on the Pentium and Pentium Pro families.






Display general register set from kdb's current task.

rd c 0
Display coprocessor 0 registers.

rm %eax 0
Set the contents of %eax to zero. This will be the value of %eax when kdb returns from the condition which invoked it.

rm %%eax 0
Set the value of the %eax register to zero. This will be the value the user-mode application will see upon returning from the kernel.

rm %acc0_h 0
Set the contents of high byte of accumulator to zero.

rm dr0 0xc1287220
Set the value of the dr0 register to 0xc1287220.

rm %InVLD_BTB 0
Write 0 to coprocessor 15 register with CRn=7, CRm=5, opcode2=6.

rm %CP15CRn7CRm5Op6 0
Same with above.