SYNOPSIS

struct drm_dp_mst_topology_mgr {
struct device * dev;
const struct drm_dp_mst_topology_cbs * cbs;
struct drm_dp_aux * aux;
int max_payloads;
int conn_base_id;
struct drm_dp_sideband_msg_rx down_rep_recv;
struct drm_dp_sideband_msg_rx up_req_recv;
struct mutex lock;
bool mst_state;
struct drm_dp_mst_branch * mst_primary;
u8 dpcd[DP_RECEIVER_CAP_SIZE];
int pbn_div;
};

MEMBERS

dev

device pointer for adding i2c devices etc.

cbs

callbacks for connector addition and destruction. max_dpcd_transaction_bytes - maximum number of bytes to read/write in one go.

aux

aux channel for the DP connector.

max_payloads

maximum number of payloads the GPU can generate.

conn_base_id

DRM connector ID this mgr is connected to.

down_rep_recv

msg receiver state for down replies.

up_req_recv

msg receiver state for up requests.

lock

protects mst state, primary, dpcd.

mst_state

if this manager is enabled for an MST capable port.

mst_primary

pointer to the primary branch device.

dpcd[DP_RECEIVER_CAP_SIZE]

cache of DPCD for primary port.

pbn_div

PBN to slots divisor.

DESCRIPTION

This struct represents the toplevel displayport MST topology manager. There should be one instance of this for every MST capable DP connector on the GPU.

AUTHORS

Jesse Barnes <[email protected]>
Intel Corporation,         
        

Initial version

Laurent Pinchart <[email protected]>
Ideas on board SPRL,         
        

Driver internals

Daniel Vetter <[email protected]>
Intel Corporation,         
        

Contributions all over the place

Lukas Wunner <[email protected]>

vga_switcheroo documentation

COPYRIGHT